1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and its manufacturing method, particularly relates to a metal oxide nitride oxide semiconductor (MONOS) nonvolatile semiconductor memory device and its manufacturing method.
2. Description of the Related Art
An MIS transistor for forming a nonvolatile storage cell is roughly classified into two types of a metal nitride oxide semiconductor (MNOS) transistor and a floating-gate (FG) transistor basically.
The former stores information charge in an interface area formed in a boundary region of two gate insulating films having two-layer structure. For this type of another device, there is a device called MONOS in which a silicon oxide film is formed on a silicon nitride film. There are also devices having structure in which insulating films except the silicon oxide film and the silicon nitride film are variously combined.
The latter stores information charge in a floating-gate electrode which is a first gate electrode in the structure of two gate electrodes. In this structure, the first gate electrode is formed on a silicon oxide film on the major surface of a semiconductor substrate in a floating state. An inter insulating layer composed of a silicon oxide film and a silicon nitride film is provided on the first gate electrode. Further, a second gate electrode which is a control gate electrode is formed on the layer insulating film. The second gate electrode covers the first gate electrode.
In a nonvolatile memory called a flash memory, the M(O)NOS transistor or the FG transistor described above can be basically used for a nonvolatile storage cell in the memory device, and the current all flash memories by quantity production use the FG transistor for a nonvolatile storage cell. However, in the FG transistor, the holding characteristic of information charge is not satisfactory in principle and a relatively thick silicon oxide film 9 nm or more thick is required for a tunneling oxide film between the major surface of a semiconductor substrate and a floating-gate electrode. Therefore, there is a limit in the reduction of voltage for writing and erasing information charge.
In the meantime, in an MNOS transistor, a tunneling oxide film between the major surface of a semiconductor substrate and a silicon nitride film can be easily thinned and a thin silicon oxide film 3 nm or less thick can be used. Therefore, operating voltage, particularly, voltage for writing and erasing information charge can be reduced. The operation for writing and erasing information charge of the nonvolatile storage cell is as follows.
That is, in the MNOS transistor, information charge is written by injecting an electron from the semiconductor substrate into the interface area directly through a tunnel of a silicon oxide film approximately 2 nm thick formed on the major surface of the semiconductor substrate and conversely, information charge is erased by emitting an electron from the interface area to the semiconductor substrate. Such an interface area functions as the center of the capture of an electron. A state in which information charge is written is equivalent to the logic 1 of stored information and a state in which information charge is erased is equivalent to the logic 0 of stored information. Then, to make the M(O)NOS transistor in which voltage for writing and erasing can be reduced in principle practicable as a storage cell of a nonvolatile memory such as a flash memory, various study has been recently made energetically.
For technique for using an MONOS transistor for a nonvolatile storage cell of a flash memory, there is technique disclosed in the U.S. Pat. No. 5,768,192 (hereinafter called as a first conventional type) and technique published on “2000 Symposium on VLSI Technology Digest of Technical Papers” pp. 122 and 123 (hereinafter called as a second conventional type), for example.
Then, for prior art, referring to FIGS. 1 to 4, the first conventional type will be first described below. FIG. 1 is a schematic sectional view showing an MONOS transistor proposed as a nonvolatile storage cell of a flash memory.
As shown in FIG. 1, a first diffused layer 102 and a second diffused layer 103 are formed by an N+-type diffused layer on the major surface of a silicon substrate 101 of a P conductive type, for example. A first silicon oxide film 104, a silicon nitride film 105 and a second silicon oxide film 106 (ONO structure) are sequentially laminated on the silicon substrate 101 between the first diffused layer 102 and the second diffused layer 103. Further, a gate electrode 107 is formed by polycrystalline silicon on the second silicon oxide film 106. This structure is the basic structure of the MONOS transistor.
Next, referring to FIGS. 2 and 3, the basic operation of the MONOS transistor will be described. For operation for writing information charge (an electron in this case), as shown in FIG. 2A, for example, the silicon substrate 101 and the first diffused layer 102 are fixed to ground potential, the voltage VW of the second diffused layer 103 is set to approximately 4 V and the voltage VGW of the gate electrode 107 is set to approximately 6 V.
When such voltage is applied, an electron stream 108 (channel current) is produced from the first diffused layer 102 which functions as a source to the second diffused layer 103 which functions as a drain, which current become a channel hot electron (CHE) in the vicinity of the second diffused layer 103 and a part thereof is captured in a certain area of the silicon nitride film 105 beyond the barrier of the first silicon oxide film 104. This area is a capture area 109 shown in FIG. 2. As described above, in writing an electron, information charge is stored in an area near to the end of the second diffused layer 103 in the silicon nitride film 105. The quantity of written electrons is approximately 500 to 1000 pieces and the capture area 109 is a very small region such that the width in the lateral direction is approximately 10 nm.
Next, for operation for erasing information in the MONOS transistor, in structure shown in FIG. 2B, for example, the silicon substrate 101 and the first diffused layer 102 are fixed to ground potential, the voltage VE of the second diffused layer 103 is set to 5 V and the voltage VGE of the gate electrode 107 is set to approximately −5 V.
When such voltage is applied, a hole generated by tunneling between bands by the bending of a band in a region at the end of the second diffused layer 103 and overlapped with the gate electrode 107 is injected into the capture area 109 and information charge is erased. That is, as shown in the drawing, the injection of a hole 110 into the capture area 109 is caused and electrons which is information charge are erased.
Next, for operation for reading information from the MONOS transistor, as shown in FIG. 3, conversely, the second diffused layer 103 is fixed to ground potential as a source, the voltage VR of the first diffused layer 102 which functions as a drain is set to approximately 1.5 V and the voltage VGR of the gate electrode 107 is set to approximately 2.5 V. The silicon substrate 101 is set to ground potential.
Hereby, in the case of logic in which electrons are written in the capture area 109, no current flows between the first diffused layer 102 and the second diffused layer 103. In the meantime, in the case of logic 0 in which no electron is written in the capture area 109, current flows between the first diffused layer 102 and the second diffused layer 103. Hereby, written information can be read.
In a state in which information is held in the MONOS transistor, as shown in FIG. 4, the silicon substrate 101 and the first diffused layer 102 are fixed to ground potential, the voltage VH of the second diffused layer 103 is set to approximately 1 to 5 V and the voltage VGH of the gate electrode 107 is set to approximately 0 to 6 V. However, in the prior art, as described later, electrons in the capture area 109 in the silicon nitride film 105 drift in the silicon nitride film 105.
Next, for the prior art, referring to FIG. 5, the second conventional type will be described. FIG. 5 is also a schematic sectional view showing an MONOS transistor proposed as a nonvolatile storage cell of a flash memory and the MONOS transistor is characterized in that a word electrode to be a word line and a control gate electrode are formed in structure in which memory cells are arrayed.
As shown in FIG. 5, a first diffused layer 202 and a second diffused layer 203 are formed by an N+-type diffused layer on the major surface of a P-conductive type silicon substrate 201, for example. A first control gate electrode 204, a second control gate electrode 205 and a word electrode 206 are formed over the silicon substrate 201 between the first diffused layer 202 and the second diffused layer 203. Insulating films between the first or second control gate electrode 204, 205 and the silicon substrate 201 are formed by insulating films having ONO structure as in the first conventional type and an insulating film between the word electrode 206 and the silicon substrate 201 is formed by a single-layer silicon oxide film. Further, the first or second control gate electrode 204, 205 and the word electrode 206 are also electrically disconnected by the insulating films having ONO structure.
In such structure, information charge (an electron) is respectively written in capture areas 207, 208 having ONO structure under the first and second control gate electrodes 204, 205. For operation for erasing information charge, voltage is applied between the first control gate electrode 204 and the first diffused layer 202 and between the second control gate electrode 205 and the second diffused layer 203, and a hole generated by tunneling between bands and described in relation to the first conventional type is injected into each capture area 207, 208.
In the nonvolatile storage cell of the first conventional type, to guarantee a specified value of time in which information charge is stored, there is a limit in thinning the first silicon oxide film 104, the silicon nitride film 105 and the second silicon oxide film 106. Currently, the inventor performs various tests and experiments of the basic characteristics of a nonvolatile storage cell having MONOS structure. As a result, it proves that to guarantee the time in which information is stored and held of 10 years, the lower limit of thinning in case insulating films having ONO structure are formed by a silicon oxide film is approximately 8 nm. In a recent flash memory in which speeding up is essential, it has proven that there is a limit in speeding up operation for reading.
Further, in the first conventional type, as described above, electrons written in the capture area 109 of information charge drift in a lateral direction in the silicon nitride film 105, the electric conduction of which is relatively high as shown by arrows in FIG. 4. Therefore, the capture area is expanded as time goes and the holding characteristic of information charge is deteriorated.
The nonvolatile storage cell having MONOS structure is used for a nitride read only memory (NROM) disclosed in the U.S. Pat. No. 5,966,603. In this case, 2-bit information can be written per cell. However, as described above, when the capture area 109 is expanded as time goes, it becomes difficult to read stored information. Particularly, even the slight variation in elapsed time of the capture area has a large effect upon NROM operated based upon multiple values. In this case, the quantity of written electrons is approximately 500 pieces and the capture area for the electrons the width in the lateral direction of which is approximately 10 nm is a very small region.
Besides, in the second conventional type, the MONOS transistor provided with the control gate electrode as described above and the MOS transistor provided with the word electrode are mounted in one memory cell. The control gate electrode is formed by a side wall conductive film formed on the side wall of the word electrode. In such structure, as the dimension in a direction of a channel of the control gate electrode can be reduced, the effective length of the channel is shortened and operation for reading can be speeding up.
However, as described above, the control gate electrode is formed on the side wall of the word electrode. Therefore, in an array of cells, a control gate electrode line and a word electrode line (the word line) are arranged in the same direction. Further, the control gate electrode line and the word electrode line are also arranged in parallel with the bit line formed by the first and second diffused layers. However, the word line and the bit line are required to be arranged perpendicularly in view of relation with a peripheral circuit of a memory cell. In the second conventional type, such a layout is difficult.
Besides, in the second conventional type, as described above, the control gate electrode is formed by the side wall conductive film formed on the side wall of the word electrode. Therefore, the width of the electrode is very narrow, when this is used for wiring, the resistance increases and the delay of transmission increases. From this viewpoint, the application to a memory cell also is difficult.
Further, in the second conventional type, as in the first conventional type, the capture area of information charge is also expanded as time goes and the holding characteristic of information charge is deteriorated.